我的晶元之路4

01-31

我的晶元之路4

上回說到將完成前仿

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建議把這篇的代碼複製到notepad++等代碼文本編輯器裡面。。。存為.v文件容易看。。。。。

部分注釋都是沒有改的。。。。讀者見諒了。。。

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通過前仿的代碼

一共的文件如上圖。

scll40nll_hs_wd_lvt_tt_v1p1_25c_ccs

sha_iptop_post

為工藝文件、綜合後的晶元文件，是要測試的內核（大概這意思）

Sha_state為主流程

module sha_state(sha_clk , sha_reset_bn,sha_rdata,monitor1,monitor2,monitor3);

parameter SHACTRL=5b01000,

SHADI0=5b10000,

SHADI1=5b10001,

SHADI2=5b10010,

SHADI3=5b10011,

SHADI4=5b10100,

SHADI5=5b10101,

SHADI6=5b10110,

SHADI7=5b10111,

SHADI8=5b11000,

SHADI9=5b11001,

SHADIA=5b11010,

SHADIB=5b11011,

SHADIC=5b11100,

SHADID=5b11101,

SHADIE=5b11110,

SHADIF=5b11111,

SHADO0=5b00000,

SHADO1=5b00001,

SHADO2=5b00010,

SHADO3=5b00011,

SHADO4=5b00100,

SHADO5=5b00101,

SHADO6=5b00110,

SHADO7=5b00111;

parameter

S4_1=5b00000,

S4_1_2=5b00001,

S4_2=5b00010,

S4_2_2=5b00011,

S4_3=5b00100,

S4_3_2=5b00101,

S4_4=5b00110,

S4_4_2=5b00111,

S4_5=5b01000,

S4_5_2=5b01001,

S4_6=5b01010,

S4_6_2=5b01011,

S4_7=5b01100,

S4_7_2=5b01101,

S4_8=5b01110,

S4_8_2=5b01111,

S4_9=5b10000,

S4_9_2=5b10001,

S4_10=5b10010,

S4_10_2=5b10011,

S4_11=5b10100,

S4_11_2=5b10101,

S4_12=5b10110,

S4_12_2=5b10111,

S4_13=5b11000,

S4_13_2=5b11001,

S4_14=5b11010,

S4_14_2=5b11011,

S4_15=5b11100,

S4_15_2=5b11101,

S4_16=5b11110,

S4_16_2=5b11111;

parameternS0=3b000,

S1=3b001,

S2=3b010,

S3=3b011,

S4=3b100,

S5=3b101,

S6=3b110,

S7=3b111;

input sha_clk n, sha_reset_b ;

outputnwire [7:0]sha_rdata;

//reg [7:0] sha_rdata_reg;

//assignnsha_rdata = sha_rdata_reg;

outputnmonitor1,monitor2,monitor3;

reg [7:0] nsha_wdata=8b0 ;

reg sha_rw_b = 1b1 ;

reg [4:0] nsha_addr =5b00000 ;

reg [1:0] npre =2b00 ;

reg sha_ipen=1b0 ;

//狀態信號

regn[2:0]current_state=3b000;

regn[4:0]S4_state=5b000;

//測試用

regnmonitor1_reg=1b0;

regnmonitor2_reg=1b0;

regnmonitor3_reg=1b0;

assignnmonitor1=monitor1_reg;

assignnmonitor2=monitor2_reg;

assignnmonitor3=monitor3_reg;

regnstartS1=1b0;

regnstartS2=1b0;

regnstartS3=1b0;

regnstartS4=1b0;

regnstartS5=1b0;

regnstartS6=1b0;

regnsign0=1b0;//S1流程式控制制信號

regnsign1=1b0;

regnsign2=1b0;

regnsign2_0=1b0;

regnsign2_1=1b0;

regnsign2_2=1b0;

regnsign2_3=1b0;

regnsign3_0=1b0;

regnsign3_1=1b0;

regnsign3_2=1b0;

regnsign3_3=1b0;

regnsign3_4=1b0;

regnsign3_5=1b0;

regnsign3_6=1b0;

regnsign3_7=1b0;

regnsign3_8=1b0;

regnsign5_0=1b0;

regnsign6_delay=1b0;

regnsign6_0=1b0;

regnsign6_1=1b0;

regnsign6_2=1b0;

regnsign6_3=1b0;

regnsign6_4=1b0;

regnsign6_5=1b0;

regnsign6_6=1b0;

regnsign6_7=1b0;

regnsign6_8=1b0;

//sha_iptop實例化

sha_iptop

nCORE (

n.sha_wdata (sha_wdata ) ,

n.sha_rw_b (sha_rw_b ) ,

n.sha_clk (sha_clk ) ,

n.sha_addr (sha_addr ) ,

n.pre (pre ) ,

n.sha_rdata (sha_rdata ) ,

n.sha_ipen (sha_ipen ) ,

n.sha_reset_b (sha_reset_b ) );

//counter實例化

regncounter_start=0;

regn[15:0]delay=0;

regncounter_reset=0;

wirencounter_stop;//counter的返回值要改為wire

wirencounter_reuse;

counternc0(.clk(sha_clk),//讀stop，stop=1時結束

.rst(counter_reset),

.start(counter_start),

.delay(delay),

.stop(counter_stop),

.reuse(counter_reuse));

//W32be實例化

regnw32be_start=0;

regnw32be_reset=0;

regn[31:0]w32be_data;

regn[4:0]w32be_addr;

wiren[7:0]w32be_sha_wdata;

wiren[1:0]w32be_pre;

wirenw32be_stop;

wirenw32be_reuse;

nW32be W32be(

.clk(sha_clk),

.rst(w32be_reset),

.start(w32be_start),

.addr(w32be_addr),

.data(w32be_data),

.pre(w32be_pre),

.sha_wdata(w32be_sha_wdata),

.stop(w32be_stop),

.reuse(w32be_reuse));

//read實例化

regnread_start=0;

regnread_reset=0;

regn[4:0]read_addr;

wiren[1:0]read_pre;

wirenread_stop;

wirenread_reuse;

nread read(

.clk(sha_clk),

.rst(read_reset),

.start(read_start),

.addr(read_addr),

.pre(read_pre),

.stop(read_stop),

.reuse(read_reuse));

always@(posedgensha_clk)

if(sha_reset_bn== 1b0)

begin

//current_state=nS1;

current_state=S0;

end

else

begin

//current_staten<=next_state;

case(current_state)

S0:begin

sign0=1b0;//重置延時標記

sign1=1b0;

sign2=1b0;

sha_ipen=1b0;

sha_rw_b=1b1;//控制讀寫信號開啟。S2可以直接W32be了

sha_addr=5b00000;

sha_wdata=8b0;

pre=2b00;

counter_start=1b0;

delay=0;

startS1=1b0;

current_state=S1;

end

S1:begin

if(startS1==1b0)

begin

counter_startn=1b1;

delayn=16h0020;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h1101;

startS1=1b1;

sign0=1b1;

counter_reset=1;

end

//信號sign0，對應 #500 nsha_ipen=1b1;

elsenif(sign0==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

delay=16h0019;//#50

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h1102;

sha_ipen=1b1;

sign0=1b0;

sign1=1b1;

counter_reset=1;

end

//信號sign1，對應#500

elsenif(sign1==1b1)

begin

counter_reset=0;

begin

counter_start=1b1;

delay=16h0019;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h1103;

sign1=1b0;

current_state=S2;

counter_reset=1;

end

// S2:W32be(SHACTRL,32h0000000a);#8000;

S2:begin

if(startS2==1b0)

begin

assignnpre=w32be_pre;

assignnsha_wdata=w32be_sha_wdata;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

/*assignn和deassign

不支持對reg 數據類型的assign或deassign進行綜合，支持對wire數據類型的assign或deassign進行綜合。*/

w32be_start=1b1;

w32be_data=32h0000000a;

// w32be_addr=SHACTRL;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

startS2=1b1;

sign2_0=1b1;

w32be_reset=1;

end

elsenif(sign2_0==1b1)

begin

w32be_reset=0;

sign2_0=0;

sign2_1=1;

deassignnpre;

deassignnsha_wdata;

end

//信號sign2_1，對應 #8000 n

elsenif(sign2_1==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

delay=16h0190;//#400;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h2200;

sign2_1=1b0;

sign2_2=1b1;

current_state=S3;

counter_reset=1;

end

S3:begin

//read(SHACTRL);

if(startS3==1b0)

begin

assignnpre=read_pre;

sha_rw_b=1b1;

read_start=1b1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

startS3=1b1;

sign3_0=1b1;

read_reset=1;

end

//nread(SHADO0);

elsenif(sign3_0==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_0=1b0;

sign3_1=1b1;

read_reset=1;

end

//nread(SHADO1);

elsenif(sign3_1==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_1=1b0;

sign3_2=1b1;

read_reset=1;

end

//nread(SHADO2);

elsenif(sign3_2==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_2=1b0;

sign3_3=1b1;

read_reset=1;

end

//nread(SHADO3);

elsenif(sign3_3==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_3=1b0;

sign3_4=1b1;

read_reset=1;

end

//nread(SHADO4);

elsenif(sign3_4==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_4=1b0;

sign3_5=1b1;

read_reset=1;

end

//nread(SHADO5);

elsenif(sign3_5==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_5=1b0;

sign3_6=1b1;

read_reset=1;

end

//nread(SHADO6);

elsenif(sign3_6==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_6=1b0;

sign3_7=1b1;

read_reset=1;

end

//nread(SHADO7);

elsenif(sign3_7==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign3_7=1b0;

sign3_8=1b1;

current_state=S4;

deassignnpre;

read_reset=1;

end

S4:

begin

if(startS4==1b0)

begin

assignnpre=w32be_pre;

assignnsha_wdata=w32be_sha_wdata;

sha_rw_b=1b1;

case(S4_state)

//W32(SHADI0,32h61626364);

S4_1:

begin

sha_addr=SHADI0;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h61626364;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_1_2;

end

S4_1_2: // #100 sha_rw_b=1b1;

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_state =nS4_2;

counter_reset=1;

end

// W32(SHADI1,32h62636465);#100 sha_rw_b=1b1;

S4_2:

begin

w32be_reset=0;

sha_addr=SHADI1;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h62636465;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_2_2;

end

S4_2_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_3;

counter_reset=1;

end

//nW32(SHADI2,32h63646566);

S4_3:

begin

w32be_reset=0;

sha_addr=SHADI2;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h63646566;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_3_2;

end

S4_3_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_4;

counter_reset=1;

end

// W32(SHADI3,32h64656667);

S4_4:

begin

w32be_reset=0;

sha_addr=SHADI3;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h64656667;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_4_2;

end

S4_4_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_5;

counter_reset=1;

end

// W32(SHADI4,32h65666768);

S4_5:

begin

w32be_reset=0;

sha_addr=SHADI4;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h65666768;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_5_2;

end

S4_5_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_6;

counter_reset=1;

end

//開始複製 W32(SHADI5,32h66676869);

S4_6:

begin

w32be_reset=0;

sha_addr=SHADI5;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h66676869;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_6_2;

end

S4_6_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_7;

counter_reset=1;

end

//nW32(SHADI6,32h6768696a);//read(SHADI6);

S4_7:

begin

w32be_reset=0;

sha_addr=SHADI6;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6768696a;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_7_2;

end

S4_7_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_8;

counter_reset=1;

end

// W32(SHADI7,32h68696a6b);//read(SHADI7);

S4_8:

begin

w32be_reset=0;

sha_addr=SHADI7;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h68696a6b;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_8_2;

end

S4_8_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_9;

counter_reset=1;

end

//W32(SHADI8,32h696a6b6c);//read(SHADI8);

S4_9:

begin

w32be_reset=0;

sha_addr=SHADI8;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h696a6b6c;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_9_2;

end

S4_9_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_10;

counter_reset=1;

end

//nW32(SHADI9,32h6a6b6c6d);//read(SHADI9);

S4_10:

begin

w32be_reset=0;

sha_addr=SHADI9;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6a6b6c6d;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_10_2;

end

S4_10_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_11;

counter_reset=1;

end

// W32(SHADIA,32h6b6c6d6e);//read(SHADIA);

S4_11:

begin

w32be_reset=0;

sha_addr=SHADIA;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6b6c6d6e;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_11_2;

end

S4_11_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_12;

counter_reset=1;

end

// W32(SHADIB,32h6c6d6e6f);//read(SHADIB);

S4_12:

begin

w32be_reset=0;

sha_addr=SHADIB;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6c6d6e6f;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_12_2;

end

S4_12_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_13;

counter_reset=1;

end

// W32(SHADIC,32h6d6e6f70);//read(SHADIC);

S4_13:

begin

w32be_reset=0;

sha_addr=SHADIC;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6d6e6f70;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_13_2;

end

S4_13_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_14;

counter_reset=1;

end

//n W32(SHADID,32h6e6f7071);//read(SHADID);

S4_14:

begin

w32be_reset=0;

sha_addr=SHADID;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h6e6f7071;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_14_2;

end

S4_14_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_15;

counter_reset=1;

end

// W32(SHADIE,32h80000000);//read(SHADIE);

S4_15:

begin

w32be_reset=0;

sha_addr=SHADIE;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h80000000;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_15_2;

end

S4_15_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

S4_staten= S4_16;

counter_reset=1;

end

// W32(SHADIF,32h00000000);//read(SHADIF);

S4_16:

begin

w32be_reset=0;

sha_addr=SHADIF;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h00000000;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

S4_state=S4_16_2;

end

S4_16_2:

begin

counter_reset=0;

counter_start=1b1;

delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h8888;//隨便一個標示

sha_rw_b=1b1;

//結束信號

S4_staten= S4_16_2;

startS4=1;

current_state=S5;

deassignnpre;

deassignnsha_wdata;

counter_reset=1;

end

endcase

end

S5:

begin

if(startS5==1b0)

begin

counter_reset=0;

counter_startn=1b1;

delayn=16h0032;//#1000ns,50個周期

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h9999;

startS5=1b1;

sign5_0=1b1;

counter_reset=1;

end

//W32(SHACTRL,32h00000009);

elsenif(sign5_0==1b1)

begin

assignnpre=w32be_pre;

assignnsha_wdata=w32be_sha_wdata;

sha_rw_b=1b1;

w32be_reset=0;

sha_addr=SHACTRL;

w32be_addr=sha_addr;

w32be_start=1b1;

w32be_data=32h00000009;

if(w32be_stop==1)//完成延時

begin

w32be_start=1b0;

sha_rw_b=1b0;//控制關閉信號

w32be_reset=1;

deassignnpre;

deassignnsha_wdata;

sign5_0=1b0;

current_state=S6;

end

S6:

begin

//read(SHACTRL);

if(startS6==1b0)

begin

assignnpre=read_pre;

sha_rw_b=1b1;

read_reset=1b0;

read_start=1b1;

sha_addr=SHACTRL;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

startS6=1b1;

sign6_delay=1b1;

read_reset=1;

end

//#14000

if(sign6_delay==1b1)

begin

counter_reset=0;

counter_startn=1b1;

delayn=16h02bc;//#14000ns,700個周期

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

delay=16h9988;

sign6_delay=1b0;

sign6_0=1b1;

counter_reset=1;

end

//nread(SHADO0);

elsenif(sign6_0==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO0;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_0=1b0;

sign6_1=1b1;

read_reset=1;

end

//nread(SHADO1);

elsenif(sign6_1==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO1;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_1=1b0;

sign6_2=1b1;

read_reset=1;

end

//nread(SHADO2);

elsenif(sign6_2==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO2;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_2=1b0;

sign6_3=1b1;

read_reset=1;

end

//nread(SHADO3);

elsenif(sign6_3==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO3;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_3=1b0;

sign6_4=1b1;

read_reset=1;

end

//nread(SHADO4);

elsenif(sign6_4==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO4;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_4=1b0;

sign6_5=1b1;

read_reset=1;

end

//nread(SHADO5);

elsenif(sign6_5==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO5;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_5=1b0;

sign6_6=1b1;

read_reset=1;

end

//nread(SHADO6);

elsenif(sign6_6==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO6;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_6=1b0;

sign6_7=1b1;

read_reset=1;

end

//nread(SHADO7);

elsenif(sign6_7==1b1)

begin

read_reset=0;//=1時reset

begin

read_start=1b1;

sha_addr=SHADO7;

read_addr=sha_addr;

if(read_stop==1)//完成延時

begin

read_start=1b0;

sign6_7=1b0;

sign6_8=1b1;

current_state=S7;

deassignnpre;

read_reset=1;

end

S7:

begin

end

endcase

end

endmodule

兩模塊sha_read,sha_write

modulenW32be(clk,rst,start,addr,data,pre,sha_wdata,stop,reuse);

inputnclk,rst,start;//clk是給counter用的。rst是自己用的，在state.v中module state中調用復用

inputn[4:0] addr;

inputn[31:0] data;//相比較原本的那個tb（不可綜合的），原來的data 8位要慢一個周期給到sha_wdata,pre也要晚一個周期傳輸到，感覺應該不會出問題

//原來w32be 的task中的#100都有在本文件中狀態機中實現

//output,復用部分信號

outputnwire stop;//stop=1時，本次計時結束

outputnwire reuse;//resure=1時，可以開始下一次計數周期

regnstop_reg=1b0;

regnreuse_reg=1b0;

assignnstop = stop_reg;

assignnreuse = reuse_reg;

//output，正常的信號控制部分

outputnwire [1:0]pre;

outputnwire [7:0]sha_wdata;

regn[1:0]pre_reg=2b00;

regn[7:0]sha_wdata_reg=8b0;

assignnpre=pre_reg;

assignnsha_wdata=sha_wdata_reg;

//給counter的控制信號

regncounter_start=0;

regn[15:0]counter_delay=0;

regncounter_reset=0;

wirencounter_stop;

wirencounter_reuse;

//狀態信號

regnsign0=1b0;

regnsign1=1b0;

regnsign2=1b0;

regnsign3=1b0;

regnsign4=1b0;

regnsign5=1b0;

regn[2:0] state=3b000;

counternw0(.clk(clk),//讀stop，stop=1時結束

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

alwaysn@ (posedge clk or posedge rst)

begin

ifn(rst)//rst=1??????????-￡??????rst=0

begin

counter_reset=1;

stop_regn= 1b0;

reuse_reg=n1b1;

staten= 3b000;

counter_start=0;

end

else

begin

case(state)

3b000:

begin

counter_reset=0;

stop_regn=1b0;

reuse_reg=1b1;

if(startn== 1b1)

begin

staten= 3b001;

reuse_reg=1b0;

sign0=1;

end

else

begin

staten= 3b000;

end

3b001:

begin

//#100; pre=adr; sha_wdata=data;

if(sign0==1b1)

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h3201;//隨便一個標示

pre_reg=2b00;

sha_wdata_reg=data[7:0];

sign0=1b0;

sign1=1b1;

staten= 3b010;

counter_reset=1;

end

3b010:

begin

//#100; pre=adr; sha_wdata=data;

if(sign1==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h3302;//隨便一個標示

pre_reg=2b01;

sha_wdata_reg=data[15:8];

sign1=1b0;

sign2=1b1;

counter_reset=1;

staten= 3b011;

end

3b011:

begin

//#100; pre=adr; sha_wdata=data;

if(sign2==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h3203;//隨便一個標示

pre_reg=2b10;

sha_wdata_reg=data[23:16];

sign2=1b0;

sign3=1b1;

counter_reset=1;

staten= 3b100;

end

3b100:

begin

//#100; pre=adr; sha_wdata=data;

if(sign3==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h3204;//隨便一個標示

pre_reg=2b11;

sha_wdata_reg=data[31:24];

sign3=1b0;

sign4=1b1;

counter_reset=1;

staten= 3b101;

end

3b101:

begin

//#100; sha_rw_b=1b0;(這個改交給modulenstate控制，在運行w32be結束後) sha_addr=adr;(這個不用了)

if(sign4==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h3232;//隨便一個標示

sign4=1b0;

sign5=1b1;

counter_reset=1;

staten= 3b110;

end

3b110:

begin

staten<=3b111;

stop_regn<= 1b1;

end

3b111:

begin

staten<=3b000;

end

endcase

end

endmodule

modulenread(clk,rst,start,addr,pre,stop,reuse);

inputnclk,rst,start;//clk是自己用&給counter用的。rst是自己用的，在state.v中module state中調用復用

inputn[4:0] addr;

//output,復用部分信號

outputnwire stop;//stop=1時，本次計時結束

outputnwire reuse;//resure=1時，可以開始下一次計數周期

regnstop_reg=1b0;

regnreuse_reg=1b0;

assignnstop = stop_reg;

assignnreuse = reuse_reg;

//output，正常的信號控制部分

outputnwire [1:0]pre;

regn[1:0]pre_reg=2b00;

assignnpre=pre_reg;

//給counter的控制信號

regncounter_start=0;

regn[15:0]counter_delay=0;

regncounter_reset=0;

wirencounter_stop;

wirencounter_reuse;

//狀態信號

regnsign0=1b0;

regnsign1=1b0;

regnsign2=1b0;

regnsign3=1b0;

regnsign4=1b0;

regnsign5=1b0;

regn[2:0] state=3b000;

counternr0(.clk(clk),//讀stop，stop=1時結束

.rst(counter_reset),

.start(counter_start),

.delay(counter_delay),

.stop(counter_stop),

.reuse(counter_reuse));

//從這開始改20160817

alwaysn@ (posedge clk or posedge rst)//rstè????aé?1?????¨????????????

begin

ifn(rst)//rst=1??????????-￡??????rst=0

begin

counter_reset<=1;

stop_regn<= 1b0;

reuse_reg<=n1b1;

staten<= 3b000;

counter_start<=0;

end

else

begin

case(state)

3b000:

begin

counter_reset<=0;

stop_regn<=1b0;

reuse_reg<=1b1;

pre_reg=2b00;

if(startn== 1b1)

begin

staten= 3b001;

reuse_reg=1b0;

sign0=1;

end

else

begin

staten= 3b000;

end

3b001:

begin

//#100; sha_addr=addr; pre=2b00;

if(sign0==1b1)

begin

counter_start=1b1;

counter_delay=10;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h4401;//隨便一個標示

pre_reg=2b00;

sign0=1b0;

sign1=1b1;

staten= 3b010;

counter_reset=1;

end

3b010:

begin

//#200; pre=2b01;

if(sign1==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=10;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h4402;//隨便一個標示

pre_reg=2b01;

sign1=1b0;

sign2=1b1;

counter_reset=1;

staten= 3b011;

end

3b011:

begin

// #200 npre=2b10;//』001狀態

if(sign2==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=10;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h4403;//隨便一個標示

pre_reg=2b10;

sign2=1b0;

sign3=1b1;

counter_reset=1;

staten= 3b100;

end

3b100:

begin

// #200 npre=2b11;

if(sign3==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=5;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h4404;//隨便一個標示

pre_reg=2b11;

sign3=1b0;

sign4=1b1;

counter_reset=1;

staten= 3b101;

end

3b101:

begin

//#200;

if(sign4==1b1)

begin

counter_reset=0;//=1時reset

begin

counter_start=1b1;

counter_delay=10;

if(counter_stop==1)//完成延時

begin

counter_start=1b0;

counter_delay=16h4405;//隨便一個標示

sign4=1b0;

sign5=1b1;

counter_reset=1;

staten= 3b110;

end

3b110:

begin

staten<=3b111;

stop_regn<= 1b1;

end

3b111:

begin

staten<=3b000;

end

endcase

end

endmodule

計數器

modulencounter(clk,rst,start,delay,stop,reuse);

inputnclk,rst;

inputnstart;

inputn[15:0] delay;//delay??°???

// inputndelay;

outputnwire stop;//stop=1時，本次計時結束

outputnwire reuse;//resure=1時，可以開始下一次計數周期

regn[15:0] counter=16h0;

regnstop_reg=1b0;

regnreuse_reg=1b0;

regn[1:0] state=2b00;

assignnstop = stop_reg;

assignnreuse = reuse_reg;

alwaysn@ (posedge clk or rst)

begin

ifn(rst)//rst=1??????????-￡??????rst=0

begin

countern<= 16h0;

stop_regn<= 1b0;

reuse_reg<=n1b1;

staten<= 2b00;

end

else

case(state)

2b00:

begin

stop_regn<=1b0;

reuse_reg<=1b1;

if(startn== 1b1)

beginn

staten<= 2b01;

reuse_regn<=1b0;

end

else

begin

stop_regn<=1b0;//stop=1???????-￠???stop=0??§??-

reuse_reg<=1b1;

end

2b01:

begin

countern<= counter + 1;

if(counter==delay)

begin

stop_regn<= 1b1;//è????°????ˉ????stop_reg=1

staten<= 2b10;

countern<=16h0;

end

2b10:

begin

// state <= 2b11;

staten<=2b00;

end

endcase

end

endmodule

對sha_state寫一個testbench做測試

這個應該作為top使用

input中應該加入state中的所有信號，每次給一個就行，不要讓state再去實例化這個就對了。

`timescale 10ns/1ps//20ns為一個周期

module sha_state_tb;

parameter S0=3b000,

S1=3b001,

S2=3b010,

S3=3b011,

S4=3b100,

S5=3b101;

reg sha_clk n;

reg sha_reset_b ;

wire [7:0] nsha_rdata ;

reg [7:0] nsha_wdata ;

reg sha_rw_b n;

reg [4:0] nsha_addr ;

reg [1:0] npre ;

reg sha_ipen n;

// wire monitor1,monitor2,monitor3;

regndelaystart=0;

regndelaystop=0;//讀的延時返回信息，stop=1時計數停止/delay完成，開始下一步

regn[15:0]delay=1;

sha_state

sha_state(n

n.sha_clk (sha_clk ) ,

n.sha_rdata (sha_rdata ) ,

n.sha_reset_b (sha_reset_b ),

.sha_wdata (sha_wdata ) ,

n.sha_rw_b (sha_rw_b ) ,

n.sha_addr (sha_addr ) ,

n.pre (pre ) ,

n.sha_ipen (sha_ipen ) ,

n*/

.monitor1(monitor1),

.monitor2(monitor2),

.monitor3(monitor3));

sha_state

DUT(n

n.sha_wdata (sha_wdata ) ,

n.sha_rw_b (sha_rw_b ) ,

n.sha_clk (sha_clk ) ,

n.sha_addr (sha_addr ) ,

n.pre (pre ) ,

n.sha_rdata (sha_rdata ) ,

n.sha_ipen (sha_ipen ) ,

n.sha_reset_b (sha_reset_b ));

/* .delaystart(delaystart), 應該不用給計數器的控制信號，在sha_statenmodule中自己定義

.delaystop(delaystop),

.delay(delay));

initialnbegin

nsha_clk = 1b0;

nforever

n#1 sha_clk = ~sha_clk ;

end

initialnbegin

sha_reset_b=1b1;

#25nsha_reset_b=1b0;

#25 sha_reset_b=1b0;

#25 sha_reset_b=1b1;

#1000000;

$stop;

end

endmodule

CTRLnDUT0 (

.clk(sys_clk),

.reset(sys_reset),

.sha_wdata (sha_wdata ) ,

n.sha_rw_b (sha_rw_b ) ,

n.sha_clk (sha_clk ) ,

n.sha_addr (sha_addr ) ,

n.pre (pre ) ,

n.sha_rdata (sha_rdata ) ,

n.sha_ipen (sha_ipen ) ,

n.sha_reset_b (sha_reset_b ),

n.stop(stop),

n.busy(busy));

SHA_IPnDUT1 (

.sha_wdata (sha_wdata ) ,

n.sha_rw_b (sha_rw_b ) ,

n.sha_clk (sha_clk ) ,

n.sha_addr (sha_addr ) ,

n.pre (pre ) ,

n.sha_rdata (sha_rdata ) ,

n.sha_ipen (sha_ipen ) ,

n.sha_reset_b (sha_reset_b ));

alwaysn#10 sys_clk = ~sys_clk;

initial

begin

sys_clkn= 0;

sys_resetn= 0;

#10000000;

$stop;

end

endmodule

需要補充的幾點是：

ü Sha_state_tb對所有sha_state的input信號的調用設為reg，所有sha_state的output設為wire，tb文件本身沒有輸入輸出

ü assign 和deassign 不支持對reg 數據類型的assign或deassign進行綜合，支持對wire數據類型的assign或deassign進行綜合。

ü counter，w32be和read的reuse控制還是沒有用到。當時的想法是留著吧，也許後面有用

出的波形

W32開始時

READ開始

可以看到read的圖rdata出現 85 6a 09ne6（見前文演算法出來的數），和預期一致。

至此與原無法綜合的tb文件完成結果一致，前仿完成

下期將開始綜合和後仿

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微博@georgeuser，一枚很可能要搞硬體的喵控的專業記錄日記。

記錄我所走過的路，願我的分享能予人一些借鑒，也願我某日再回頭時能再拾起細節。